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2000-01, rel. 02 microcontrollers apnote ap3219 additional file apxxxx01.exe available how to use the watchdog timer of the TRICORE infineon TRICORE 32-bit microcontrollers provide a watchdog timer (wdt) on-chip. this application gives hints and examples for in-system programming of the wdt and describes the wdt protocol. authors: thomas bliem, cq nguyen / infineon smi md apps
how to use the watchdog timer of the TRICORE 2 of 17 ap3219 rel.02 1 overview ................................................................................................................3 2 wdt initialization ..................................................................................................4 2.1 default values .........................................................................................................4 2.2 time out mode .......................................................................................................4 2.3 servicing the wdt ..................................................................................................5 3 the access to the wdt registers .......................................................................6 3.1 password access ....................................................................................................6 3.2 modify access .........................................................................................................7 3.3 wrong register access ............................................................................................8 4 how to change the wdt registers......................................................................9 4.1 how to change the wdtcon0 ...............................................................................9 4.2 how to change the wdtcon1 .............................................................................10 4.3 normal timer period .............................................................................................10 5 using the wdt ....................................................................................................11 6 extended security thoughts .............................................................................12 6.1 multiple service sequences..................................................................................12 6.2 single service sequence ......................................................................................13 6.3 password access using extended security thoughts ..........................................14 7 wdt register overview......................................................................................15 ap3219 apnote ? revision history actual revision : rel.02 previous revision: rel.01 page of actual rel. page of prev. rel. subjects changes since last release all all logo changed to infineon
how to use the watchdog timer of the TRICORE 3 of 17 ap3219 rel.02 1 overview the TRICORE watchdog timer provides a recovery mechanism from software or hardware failure. the watchdog timer can either be used in an application, with its highly reliable and secure watchdog function, or it can be disabled. if the software fails to service this timer correctly, the TRICORE is reset. when the software is configured to always service the watchdog timer before it overflows, the watchdog timer will time-out if the program does not progress properly. the watchdog timer also times out if the software error was due to hardware-related failures. this operation prevents the controller from malfunctioning for longer than a user-specified time. service of the watchdog timer is a critical system function, because unintentional service due to an error condition could disable the watchdog function. thus, the TRICORE?s watchdog service requires a special instruction sequence with a password mechanism in order to become effective. incorrect sequences also lead to a reset of the chip. in order for software to determine the cause of a watchdog failure, first the watchdog timer generates a nmi trap, then the reset occurs after a certain time-out period. in the nmi trap routine, critical system state such as the pc value, the stack pointer, and context pointers can be stored to data memory for examination after the reset has occurred. the watchdog timer also has flags that indicate the type of watchdog failure. in addition to the watchdog function, a watchdog timer control register contains the wdtcon0.endinit bit, which controls access to system critical registers. the state of the endinit bit can be modified; however, this must be performed using the sophisticated password scheme of the watchdog timer. the watchdog timer monitors modifications of the endinit bit such that after clearing endinit, the watchdog timer enters a defined time-out mode; endinit must be set again before the time-out expires. in systems where the watchdog function is not applicable, the watchdog timer can be disabled. however, this operation is also protected via the password scheme. the watchdog time-out function invoked on modifications of the endinit bit is independent of the disable or enable status of the watchdog timer.
how to use the watchdog timer of the TRICORE 4 of 17 ap3219 rel.02 2 wdt initialization after a reset, the wdtcon0.endinit bit is cleared, giving access to critical system registers protected via the endinit bit. wdtcon1, used to control the operation of the watchdog timer, is one of the registers protected by endinit. when changing the operation of the watchdog timer through the controls in register wdtcon1, these changes have no immediate effect. they go into effect only after the endinit bit has been set to 1 again. in this way, changes of these bits do not interfere with the time-out operation of the wdt. because the wdt is in the time-out mode after reset, there is a time limit of 65536 system clocks on the initialization of the critical system registers. the endinit bit must be set to 1 before the time-out expires. 2.1 default values after a reset, the contents of the watchdog timer registers are as shown in table 2. table 2 watchdog timer default values after reset register default contents description wdtcon0 [31:16] 1111 1111 1111 1100 [15:0] 0000 0000 0000 0010 reload value is 0xfffc, wdtpw is 0; wdtcon0 is locked (wdtlck=1); endinit is 0, so access to endinit-protected registers is enabled. wdtcon1 [31:16] 0000 0000 0000 0000 [15:0] 0000 0000 0000 0000 watchdog timer disable request is 0; input clock request set to fsysclk/16384. wdtsr [31:16] 1111 1111 1111 1100 [15:0] 0000 0000 0001 00xx the watchdog counter contains 0xfffc (the initial time-out value); wdt is operating in time-out mode (wdtto=1); wdt is enabled (wdtds=0); input clock is fsysclk/16384. bits wdtoe and wdtae are set to 0 after a power-on hardware reset or software reset. in case of a reset caused by the wdt, these two bits are set depending on the error condition that caused the watchdog reset. 2.2 time out mode and reset pre-warning mode time-out mode is automatically triggered by the following events: ? reset ? wdtcon0 is unlocked by a successful password access time-out mode is indicated by wdtsr.wdtto=1. as the name suggests, time-out mode lasts for a particular duration, called the time-out period. time-out mode must be exited before this period is over, or the system is reset. to disable the time-out mode, bit endinit in register wdtcon0 must be written to 1 with a modifying access. this access stops the time-out, resets bit wdtsr.wdtto, and switches the wdt back to the operation determined through wdtsr.wdtds, wdtsr.wdtis and wdtcon0.wdtrel. if wdtds=1, the watchdog timer is reset to 0 and is stopped. if wdtds=0, the watchdog timer is set to the value of wdtcon0.wdtrel and starts counting upwards with the clock input selected through wdtis.
how to use the watchdog timer of the TRICORE 5 of 17 ap3219 rel.02 if the time-out mode is not properly stopped, the wdt overflows from 0xffff to 0x0000 and enters the reset pre-warning mode. this mode, indicated through bit wdtsr.wdtpr=1, is similar to the time-out mode except that it is no longer possible to stop the time-out period. note: even when the wdt is disabled and endinit is not set to 1 the watchdog timer is automatically set to time-out mode. reset pre-warning mode is automatically triggered by the following events: ? watchdog overflow error (wdtsr.wdtoe=1) ? watchdog access error (wdtsr.wdtae=1) in this mode a nmi trap request to the cpu is activated. the nmisr.nmiwdt bit in the nmi status register is set. when the watchdog timer again overflows from 0xffff to 0x0000, a reset will occur. in this mode, a nmi trap routine can save critical system state such as the pc value, the stack pointer, and context pointers can be stored to data memory for examination after the reset has occurred. the watchdog timer also has flags that indicate the type of watchdog failure. this function is especially important during program debugging. in the nmi routine, a check of the bit nmisr.nmiwdt should always be performed to distinguish the nmi trap cause from an external nmi request. note: nmiwdt has to be reset by software. 2.3 servicing the watchdog timer if the watchdog timer is used in an application and is enabled (wdtsr.wdtds=0), it must be regularly serviced to prevent it from overflowing. service is performed in two steps. first, the proper password must be written to wdtcon0 to unlock it. password access to wdtcon0 automatically switches the wdt to time-out mode. thus, the modifying access must be performed before the time-out expires or a system reset will result. during the following modifying access, the strict requirement is that wdtcon0.endinit as well as bit 1 and bits 7:4 are written with 1?s, while bits 3:2 are written with 0?s, as shown in the chapter modify access.
how to use the watchdog timer of the TRICORE 6 of 17 ap3219 rel.02 changes to the reload value wdtcon0.wdtrel, or the user-definable password wdtcon0.wdtpw, are not required. however, changing wdtpw is recommended so that software can monitor watchdog timer service operations throughout the duration of an application program. if wdt service is properly executed, time-out mode is terminated, and the watchdog timer switches back to its former mode of operation, and wdt service is complete. 3 the access to the watchdog timer registers wdtsr is a read-only register and can be read at any time. write accesses to this register have no effect (no error is reported in such a case). updating of the status bits in register wdtsr is handled automatically in hardware. the two error flags, wdtcon1.wdtoe and wdtcon1.wdtae, are not cleared through a watchdog reset (but through any other reset). they are cleared with a successful access to wdtcon0 which sets endinit to 1. wdtcon1 can also be read at any time without any restrictions. writing to this register is only possible if bit endinit is cleared to 0 (wdtcon1 is endinit-protected). updates made to the bits in this register will go into effect after endinit has been set to 1 again. access to wdtcon0 can be for any combination of the following reasons: ? to perform routine service to forestall a watchdog timer overflow ? to change fields in wdtcon0 ? to change fields in wdtcon1 ? to change other endinit-protected system registers all of these require unlocking wdtcon0 first. proper access to wdtcon0 always requires two write accesses. the first write, called the password access, unlocks wdtcon0. the second write, called the modifying access, can change values in wdtcon0. when the modifying access completes, wdtcon0 is locked again automatically. if the modifying access sets wdtcon0.endinit to 0, then other protected system registers, such as wdtcon1, are unlocked and can be modified. 3.1 password access the password required to unlock wdtcon0 is comprised of the state of bits in wdtcon0 and wdtcon1, as indicated in table 3: table 3 password requirements password bit required value 0 state of endinit in register wdtcon0 1 inverted state of wdtlck in register wdtcon0 2 state of wdtir in register wdtcon1 3 state of wdtdr in register wdtcon1 7:4 always 1 15:8 value of wdtpw in register wdtcon0 31:16 value of wdtrel in register wdtcon0
how to use the watchdog timer of the TRICORE 7 of 17 ap3219 rel.02 due to the requirements for some of the password bits, the password can never be determined just by reading the contents of the watchdog registers. a modifying step that alters some of the bits is required in order to get the right password. this password has to be written to the address location of wdtcon0 in order to unlock this register for modifications. if the password matches the requirements, register wdtcon0 is unlocked after this write operation has finished. this unlocked condition is indicated by wdtcon0.wdtlck=0. now, the following write access can modify register wdtcon0. after this write has finished, wdtcon0 is automatically locked again. wdtlck is set to 1 by hardware. if the password value written to wdtcon0 during the password access does not match the contents of wdtcon0, a watchdog access error situation exists. the watchdog error situations are detailed in the section entitled ?watchdog error conditions" further below. the following program in c-code is an example how to unlock the register wdtcon0. it can be included as a procedure in the mainfunction: //password access to unlock wdtcon0 include this in your project void wdt_passwd(void) { #define wdtcon0 *((volatile unsigned int*) 0xf0000020) #define wdtcon1 *((volatile unsigned int*) 0xf0000024) unsigned int passwd; passwd = wdtcon0; //load value from wdtcon0 passwd = passwd | 0x0f0; //sets bit 7:4 to 1 passwd = (wdtcon1 & 0x00c) //bit 2:3 from wdtcon1 | (passwd & 0xfffffff3); //and bit 2:3 cleared from wdtcon0 passwd = (passwd ^ 0x00000002); //invert bit 1 wdtcon0 = passwd; //write password to wdtcon0 } //procedure call wdt_passwd(); after this password sequence the wdtcon0 will be unlocked and you can change it by a modify access. 3.2 modify access during the modifying access, the only strict requirement is that bits 1 and 7:4 are written to 1?s, and bits 3:2 are written to 0?s. all other bits can be set to user-definable values. if the value written to wdtcon0 during the modifying access does not match these requirements, a watchdog access error exists. the watchdog error situations are detailed in the section entitled ?watchdog error conditions" further below.
how to use the watchdog timer of the TRICORE 8 of 17 ap3219 rel.02 the following program in c-code is an example how to change the register wdtcon0. it can be included as a procedure in the mainfunction: //modify access to wdtcon0 include this in your project void wdt_modify(unsigned long modify, unsigned long mask) { #define wdtcon0 *((volatile unsigned int*) 0xf0000020) unsigned int newvalue; //by the mask selected bits will be changed by the variable modify newvalue = wdtcon0 & (~mask)); newvalue = newvalue | (modify & mask); newvalue = ((0xf2 | newvalue) & (0xfffffff3)); //bit 1 and 7:4 are //written to 1?s and bit 3:2 written to 0?s wdtcon0 = newvalue; //write newvalue to wdtcon0 } now you can call the above mentioned procedure with the following instructions: mask = 0x0000000f; //bits that will be changed set to 1 modify = 0x0000000f; //new value for wdtcon0, endinit will be set to wdt_modify(modify, mask); //procedure call note: the values of the variables ?mask? and ?modify? can be changed. this is only an example and is described in the section entitled ?how to change the wdtcon0?. 3.3 watchdog error conditions there are two classes of watchdog timer errors: ? watchdog access error: an incorrect access to wdtcon0 was attempted ? watchdog timer overflow error: the wdt counter overflowed the watchdog access error status flag, wdtsr.wdtae, is set in case of an access error. a watchdog access error is generated when: ? an illegal password is supplied during password access to register wdtcon0 ? improper guard bits are supplied during a modifying access to wdtcon0 the watchdog overflow error status flag, wdtsr.wdtoe, is set if an overflow error occurs. a watchdog timer overflow error is generated if the wdt counter overflows. in all error cases, the watchdog timer: ? generates an nmi trap request ? enters the reset pre-warning mode ? sets the watchdog reset pre-warning flag, wdtsr.wdtpr and watchdog time-out period indication flag, wdtsr.wdtto note: when reset is caused by the wdt, the two error flags, wdtsr.wdtoe and wdtsr.wdtae, are not cleared. this allows the wdt to detect the double watchdog error condition. any other reset cause will clear these error flags. they are also cleared when wdtcon0.endinit is set to 1.
how to use the watchdog timer of the TRICORE 9 of 17 ap3219 rel.02 4 how to change the watchdog timer registers 4.1 how to change the wdtcon0 the first step to change the wdtcon0 register is to unlock it with the password access by a procedure as stated further above. this unlocked condition is indicated by wdtlck=0. the register wdtcon0 is now unlocked and you can proceed with a modify access. it is recommended to use the procedure wdt_modify(mask, modify) further above, in order to avoid protocol errors. the following tables will show you how to set the values of the variables ?mask? and ?modify?. the result values for the variables ?mask? and ?modify? must be combined by a disjunction of the individual values. note: you can configure only the wdtcon registers. table 4 how to set the variable mask which value do you want to change? required value for variable ?mask? endinit 0x0000 000f reload value 0xffff 0000 user-definable password 0x0000 ff00 example result value for the variable ?mask? to change the value of endinit and the reload value (combined by a disjunction of the individual values) 0xffff 000f table 5 how to set the variable modify value of the variable value required value for variable ?modify? endinit 0 1 0x0000 0000 0x0000 000f reload value yyyy is a user-definable hexvalue of 16bit from 0x0000 to 0xffff (see chapter ?normal timer period? for hints) yyyy 0xyyyy 0000 user-definable password zz is a user-definable hexvalue of 8bit from 0x00 to 0xff (see chapter ?extended security? for hints how to set this value) zz 0x0000 zz00 example result value for the variable ?modify? to change the value of the endinit bit to 1 and the reload value to 0xabcd (combined by a disjunction of the individual values) 0xabcd 000f now you can use the procedure wdt_modify(mask, modify) with the calculated values. the register wdtcon0 will be changed and locked after this access again.
how to use the watchdog timer of the TRICORE 10 of 17 ap3219 rel.02 example: mask = 0xffff000f; //bits that will be changed set to 1 modify = 0xabcd000f; //new value for wdcon0(here endinit will be set to 1 //and reset value to 0xabcd) wdt_modify(modify, mask); //procedure call 4.2 how to change the wdtcon1 writing to the register wdtcon1 is only possible if bit endinit is cleared (wdtcon1 is endinit-protected). you can change only the watchdog timer input frequency request control bit (wdtir) and the watchdog timer disable request control bit (wdtdr). symbol position type value function wdtdr wdtcon1[3] rw 0 1 watchdog timer disable request control bit. request to enable the watchdog timer. request to disable the watchdog timer. as long as endinit is 0, bit wdtds in register wdtsr controls the current enable/disable status of the watchdog timer. when endinit is 1, wdtds is updated with the state of bit wdtdr. wdtir wdtcon1[2] rw 0 1 watchdog timer input frequency request control bit. request to set input frequency to f sysclk /16384. request to set input frequency to f sysclk /256. as long as endinit is 0, bit wdtis in register wdtsr controls the current input frequency of the watchdog timer. when endinit is 1, wdtis is updated with the state of bit wdtir. note: updates made to the bits in this register will go into effect after wdtcon0.endinit has been set to 1 again. 4.3 normal timer period the duration of normal timer mode can be varied by two parameters: the input clock and the reload value. the system clock, f sysclk , can be divided by either 256 or 16384. wdtsr.wdtis selects the input clock divider. the default value of wdtis after reset is 0, corresponding to a frequency of f sysclk /16384. when the watchdog timer is serviced in normal timer mode, it is reloaded with the 16-bit reload value, wdtcon0.wdtrel. the watchdog timer period can be varied over a wide range. the maximum time period is achieved by setting wdtrel=0x0000. the minimum time period is achieved by setting wdtrel=0xffff. the general form with variable reload value wdtrel for these calculations is: period = (2 16 ? wdtrel) * 256 * 2 (1 - wdtis) * 6 / f sysclock example: wdtrel = 0xfffc = 65532; wdtis = 1; f sysclock = 100mhz; period = (2 16 ? wdtrel) * 256 * 2 (1 - wdtis) * 6 / f sysclock period = (2 16 ? 65532) * 256 * 2 (1 - 1) * 6 / 100mhz) = 10,24 s
how to use the watchdog timer of the TRICORE 11 of 17 ap3219 rel.02 5 using the watchdog timer normally, an embedded application program is built around a loop of routines, which are repeatedly executed. for example, consider the configuration in the figure shown below. this illustrates a program which, after reset, carries out whatever initialization is required. then it proceeds to a loop of routines that are executed over and over again. besides this main loop, there is a set of interrupt service routines (these are not shown in the following figures). within the loop of the mainline program, the watchdog timer service sequences are embedded. of course, also an initialization of the watchdog must be made if a different time-out value than the default one is desired. the wdt service should be placed properly in the application such that a safe service before the next overflow is guaranteed. the service should normally be performed in the main routine. placing the service sequence into an interrupt routine could cause that the wdt service will be executed even if the main program goes awry. this could disable the intended monitoring function of the watchdog timer. figure 1 standard wdt service return return return return service routine subroutines subroutines service routine int 1 service routine int 2 service routine int 3 subroutines init wdt-6 reset int n
how to use the watchdog timer of the TRICORE 12 of 17 ap3219 rel.02 wdtpw:=14h wdtpw:=12h wdt service 4 wdtpw:=13h wdtpw:=12h wdtpw:=13h wdtpw:=14h wdt service 3 wdt service 2 subroutines subroutines wdtpw:=00h wdtpw:=12h wdt service 1 subroutines init wdt-4 reset 6 extended security thoughts to increase the security of the wdt functionality, there are different possibilities how to handle these watchdog services, described in the following sections. in the associated figures, only the update of the password field wdtpw in register wdtcon0 is shown. 6.1 multiple service sequences one option is to place several service sequences inside the main code. in order to monitor the program flow, one changes the wdt password within each of the service sequences, as shown in figure 2. since at the beginning of each sequence, first the old password has to be written to wdtcon0, a link to the previous service is performed. if due to an error, one or more of the service sequences are skipped, wdtcon0 will not contain the expected value at the beginning of the next service sequence: an watchdog timer access error will occur and the bit wdtae is set. this will also happen if a service sequence is executed twice due to an erroneous loop. of course, with this scheme, the service sequences must be placed at points in the code, which are always executed during the main loop. if you want to use this feature in your application you have to use the procedure wdt_pass_secure(oldpassword) further below. figure 2 sequence of watchdog timer services
how to use the watchdog timer of the TRICORE 13 of 17 ap3219 rel.02 wdt service 2 wdtpw:=tmp wdtpw:=tmp+2 tmp = tmp+1 tmp = tmp+1 subroutines subroutines wdtpw:=12h wdtpw:=00h tmp = 10h wdt service 1 subroutines init wdt-5 reset 6.2 single service sequence another way is to place only one watchdog service sequence inside the program, normally at the end of the main loop (see figure 3). here, again monitoring of the program flow can be achieved if one uses a temporary variable, tmp, which is modified appropriately at different points during the code execution. at the end of the loop, the content of this variable is used as the wdt password. if everything was ok, the tmp value exactly matches the password value stored in wdtcon0. however, if one or several checkpoints in the code have been missed due to failures, tmp does not contain the correct value and an early watchdog time-out will be generated, setting the bit wdtsr.wdtae. if you want to use this feature in your application you have to use the procedure wdt_pass_secure(oldpassword) further below. figure 3 servicing the wdt at the end of the program loop
how to use the watchdog timer of the TRICORE 14 of 17 ap3219 rel.02 6.3 password access using the extended security thoughts the following procedure is nearly the same as the procedure used in chapter password access. the great difference is the variable hand over to the procedure. if these variable does not match with the password already stored in wdtcon0.wdtpw a watchdog timer access error (wdtsr.wdtae) will occur. in all error cases, the watchdog timer: ? generates an nmi trap request ? enters the reset pre-warning mode ? sets the watchdog reset pre-warning flag, wdtsr.wdtpr and watchdog time-out period indication flag, wdtsr.wdtto //password access to unlock wdtcon0 using the extended security thoughts //include this in your project void wdt_pass_secure(unsigned char oldpass) { #define wdtcon0 *((volatile unsigned int*) 0xf0000020) #define wdtcon1 *((volatile unsigned int*) 0xf0000024) unsigned int passwd; passwd = wdtcon0; //load value from wdtcon0 in variable passwd = passwd & 0xffff00ff; //bits from the wdtpw cleared passwd = passwd | (oldpass << 8); //value from variable included passwd = passwd | 0x0f0; //sets bit 7:4 to 1 passwd = wdtcon1 & 0x00c) //bit 2:3 loaded from wdtcon1 | (passwd & 0xfffffff3); //and bit 2:3 cleared from wdtcon0 passwd = (passwd ^ 0x00000002); //invert bit 1 wdtcon0 = passwd; //write password to register wdtcon0 } the following procedure call will unlock the wdtcon0 register if the value of the variable oldpassword does match with the password already stored in wdtcon0.wdtpw. if not, an error will occur and the wdt will enter in the reset pre-warning mode. //procedure call wdt_pass_secure(oldpassword);
how to use the watchdog timer of the TRICORE 15 of 17 ap3219 rel.02 7 wdt register overview three registers are provided with the watchdog timer unit (wdt): wdtcon0, wdtcon1, and wdtsr. table 1 wdt address map address name description block read write 0xf000 0028 wdtsr watchdog timer status register pwr u; sv u; sv; nc 0xf000 0024 wdtcon1 watchdog timer control register 1 pwr u; sv sv; e 0xf000 0020 wdtcon0 watchdog timer control register 0 pwr u; sv sv; pw wdtcon0 watchdog control register reset value: 0xfffc.0002 symbol position type value function wdtrel wdtcon0[31:16] rw reload value for the watchdog timer. if the watchdog timer is enabled, it will start counting from this value after a correct watchdog service. this field must be written with the same value during a password access. it can be modified during a modify access to wdtcon0. wdtpw wdtcon0[15:8] rw user-definable password field for access to wdtcon0. must be written with the same value during a password access. it can be modified during a modify access to wdtcon0. wdthpw1 wdtcon0[7:4] w hardware password 1. this field must be written to 1111b during both, a password access and a modify access to wdtcon0. when read these bits always return 0. wdthpw0 wdtcon0[3:2] w hardware password 0. this field must be written to the value of bits wdtdr and wdtir in register wdtcon1 during a password access. wdthpw0 must be written to 00b during a modify access to wdtcon0. when read, these bits always return 0. wdtlck wdtcon0[1] rw 0 1 lock bit to control access to wdtcon0. register wdtcon0 is unlocked. register wdtcon0 is locked. wdtlck must be reset to 0 during the password access to wdtcon0 and set to 1 during the modify access to wdtcon0 (the inverted value of wdtlck always must be written to this bit). wdtlck is controlled by hardware and is cleared after a successful password access to wdtcon0 and automatically set again after a successful modify access to wdtcon0. the value written to this bit location is only used for the protection mechanism and is not stored. endinit wdtcon0[0] rw 0 1 end-of-initialization control bit. access to endinit-protected registers is permitted. access to endinit-protected registers is not permitted. endinit controls the access to critical system registers. must be written with the same value during a password access.can be modified during a modify access to wdtcon0.
how to use the watchdog timer of the TRICORE 16 of 17 ap3219 rel.02 wdtcon1 watchdog control register 1 reset value: 0x0000.0000 symbol position type value function wdtdr wdtcon1[3] rw 0 1 watchdog timer disable request control bit. request to enable the watchdog timer. request to disable the watchdog timer. this bit can only be modified if endinit is reset to 0. an update of this bit only goes into effect when endinit is set to 1 again. as long as endinit is 0, bit wdtds in register wdtsr controls the current enable/disable status of the watchdog timer. when endinit is 1, wdtds is updated with the state of bit wdtdr. wdtir wdtcon1[2] rw 0 1 watchdog timer input frequency request control bit. request to set input frequency to f sysclk /16384. request to set input frequency to f sysclk /256. this bit can only be modified if endinit is reset to 0. an update of this bit only goes into effect when endinit is set to 1 again. as long as endinit is 0, bit wdtis in register wdtsr controls the current input frequency of the watchdog timer. when endinit is 1, wdtis is updated with the state of bit wdtir. sckclr wdtcon1[10:8] rw self check clear request bits. sckclr = : request to clear bit sckerr[]. when endinit is set to 1, the corresponding bit sckerr in register wdtsr will be cleared. - r these bit positions are read-only, returning 0 when read. writing to these bit positions has no effect. these positions are reserved for future extensions, and it is advised to always write a 0 to these bit positions when writing to the register in order to preserve compatibility with future derivatives. wdtsr watchdog status register reset value: 0xfffc.uu1u symbol position type value function wdttim wdtsr[31:16] r reflects the current contents of the watchdog timer. sckerr wdtsr[15:8] r self check error bits. sckerr[] = 0: self check passed successfully. sckerr[] = 1: self check not passed this bits are set to 1 after reset when the self check configuration has been selected. each bit of this array can be cleared 1 by 1 through the sckclr bits in register wdtcon1. this operation will go into effect after endinit is written to 1 during a modify access to register wdtcon0. it is not possible to terminate the self check mode until all sckerr bits are cleared.
how to use the watchdog timer of the TRICORE 17 of 17 ap3219 rel.02 wdtpr wdtsr[5] r 0 1 watchdog reset prewarning flag. normal mode (default after reset). a watchdog error has occurred. the watchdog has issued an nmi trap and is in the final time-out phase (wdtto is also set in this case). a reset of the chip occurs after the time-out has expired. this bit can be examined in the nmi trap routine to determine the cause of the trap. wdtpr is cleared only through a reset. wdtto wdtsr[4] r 0 1 watchdog time-out period indication flag. normal mode. the watchdog is operating in time-out mode (default after reset). time-out mode is entered automatically after a reset and after the first password access to register wdtcon0 or when a watchdog error is detected. time-out mode is terminated only in a non-error case with a modify access to wdtcon0 writing endinit to 1. after termination of the time-out mode, wdtto is cleared through hardware. if time-out mode is entered due to a watchdog error, this mode cannot be terminated until the watchdog reset occurs. wdtds wdtsr[3] r 0 1 watchdog enable/disable bit. watchdog timer is enabled (default after reset). watchdog timer is disabled. this bit is updated with the state of bit wdtdr after endinit is written to 1 during a modify access to register wdtcon0. wdtis wdtsr[2] r 0 1 watchdog input clock status bit. watchdog timer input clock is f sysclk /16384 (default after reset). watchdog timer input clock is f sysclk /256. this bit is updated with the state of bit wdtir after endinit is written to 1 during a modify access to register wdtcon0. wdtoe wdtsr[1] r 0 1 watchdog overflow error status flag. no watchdog overflow error. an watchdog overflow error has occurred. this bit is set by hardware when the watchdog timer is enabled and is not serviced before the overflow from 0xffff to 0x0000 occurs, or if the watchdog timer is in time-out mode and the overflow occurs. this bit is only reset through: - a power-on, hardware, or software reset; - after endinit is written to 1 during a modify access to register wdtcon0 (not possible if watchdog is in the reset prewarning phase, wdtpr = 1). wdtae wdtsr[0] r 0 1 watchdog access error status flag. no watchdog access error. an watchdog access error has occurred. this bit is set by hardware when an illegal access to register wdtcon0 was attempted (either a password or modifying access). this bit is only reset through: - a power-on, hardware, or software reset; - after endinit is written to 1 during a modify access to register wdtcon0 (not possible if watchdog is in the reset prewarning phase, wdtpr = 1). - r these bit positions are read-only, returning 0 when read. writing to these bit positions has no effect. these positions are reserved for future extensions, and it is advised to always write a 0 to these bit positions when writing to the register in order to preserve compatibility with future derivatives.

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